The creation of complex integrated circuits and semiconductor devices can be a very expensive undertaking given the large number of hours of sophisticated engineering talent involved in designing such devices. Additionally, integrated circuits can include read only memories and/or EEPROMs into which software, in the form of firmware, is encoded. Additionally, integrated circuits are often used in applications involving the encryption of information. Therefore, in order to keep such information confidential (i.e. design, critical information and encryption), it is desirable to keep such devices from being reverse engineered. Thus, there are a variety of reasons for protecting integrated circuits and other semiconductor devices from being reverse engineered.
In order to keep the reverse engineer at bay, different techniques are known in the art to make integrated circuits more difficult to reverse engineer. One technique is to alter the composition or structures of the transistors in the circuit in such a way that the alteration is not easily apparent, forcing the reverse engineer to carefully analyze each transistor (in particular, each CMOS transistor pair for CMOS devices), and thwarting attempts to use automatic circuit and pattern recognition techniques in order to reverse engineer an integrated circuit. Since integrated circuits can have hundreds of thousands or even millions of transistors, forcing the reverse engineer to carefully analyze each transistor in a device can effectively frustrate the reverse engineer's ability to reverse engineer the device successfully.
A conductive layer, such as silicide, is often used during the manufacturing of semiconductor devices. In modern CMOS processing, especially with a feature size below 0.5 μm, a silicide layer is utilized to improve the conductivity of gate, source and drain contacts. In accordance with general design rules, any active region providing a source or drain is silicided. This silicide layer is very thin and difficult for the reverse engineer to see. Hence, if there are ways to modify the transistor through the modification of the silicide layer so as to change the transistor functionality then the modification would be difficult to determine.
FIG. 1 depicts a prior art modern CMOS device. In this example, the substrate 20 is a p-type substrate. Referring to the NMOS device, active regions 4, 6 disposed in the substrate 20 have n-type conductivity. The light density dopant (LDD) regions 14 have the same conductivity type as active regions 4, 6, but with a much lower dose than active regions 4, 6. The gate comprises a gate oxide layer 8, and a self-aligned polysilicon gate 10. Oxide sidewall spacers 16 form the differentiation between the active regions 4, 6 and the LDD regions 14. Field oxide 2 provides separation between transistors. Referring to the PMOS device, a well 21 of n-type conductivity is disposed in the substrate 20. Active regions 23, 25 having p-type conductivity are disposed within n-type well 21. LDD regions 15 have the same conductivity type as active regions 23, 25, but with a much lower dose than active regions 23, 25. The gate comprises a gate oxide layer 8, and a self-aligned polysilicon gate 10. Oxide sidewall spacers 16 form the differentiation between the active regions 23, 25 and the LDD regions 15. The silicide layer 12, is deposited and sintered over the active regions 4, 6, 23, 25 to make better contact. The silicide layer 12, is optionally deposited over the poly gates 10 as well. For the prior art CMOS device of FIG. 1, the NMOS or PMOS transistors normally turn “ON” when a voltage is applied to V1 51 or V2 50, respectively.
Many prior art techniques for discouraging or preventing reverse engineering of a circuit cause the IC to look different from a standard IC. Techniques are needed in which the transistors, and thus the circuits, are constructed to look essentially the same as conventional circuits, but where the functionality of selected transistors, and hence their circuits, is varied. The minor differences between the conventional circuit and the modified circuit should be difficult to detect by reverse engineering processes. In addition, the techniques should strive to modify only a vendor's library design instead of forming a completely new and differently appearing library. Requiring only modification to an existing library results in a simpler path to implementation.